The present invention relates to a technique of implementing a test mode in a variety of devices, including integrated circuits.
The use of test techniques to test electrical circuitry allows various diagnostic procedures to be performed on integrated circuit devices. Testing performed on integrated circuit devices validate and/or debug various component parts as part of a validation procedure when the devices are manufactured. For example, when an integrated circuit device is manufactured, validation tests are performed on the product to ensure that the manufactured component operates properly. Debugging features of a test procedure also allows various states to be monitored while the component is subjected to operating conditions. For example, as part of a debugging procedure, output lines from an integrated circuit may be monitored to determine the nature of the error and/or to localize the error to a particular circuitry or operation.
Generally, integrated circuit chips enter a test mode simply by having signals present on some combination of input pins to the integrated circuit. In this instance, the signals indicate the particular test to be performed, and the integrated circuit is activated into a particular test based on the signals at the selected combination of input pins. The signals initiate a selected test, and subsequent output is then generated in response to the performed test. With these types of testing procedures, the integrated circuit enters the particular test state with the test signal. The various state signals generated, including output states, are in response to the sequence of operations performed as part of the particular test procedure.
Although these procedures allow testing to be performed on a device, these procedures do not allow for the integrated circuit to toggle between a given test procedure and a normal operative state of the integrated circuit. Although continuous test procedures are applicable for verification and debugging of integrated circuits, a need exists to have a scheme, which allows a particular test procedure to be interrupted and toggled between the test mode and the normal operative mode.
A test mode control unit of an integrated circuit has a sample and hold circuit to receive a test mode signal upon occurrence of a reset condition to perform a selected test of the integrated circuit in response to the test mode signal. A decoder decodes the test mode signal and generates a decoded control signal to control test circuitry of the integrated circuit to perform the selected test. A logical circuit receives the decoded control signal and a test signal. The logical circuit initiates the selected test if the test signal indicates a test state but maintains the integrated circuit in its normal non-test state if the test signal does not indicate the test state. The test signal allows toggling between test and non-test modes of operation for the integrated circuit.